In the transmission of frames or packets over communication channels, errors are frequently introduced into transmitted data. A known technique of error control is error detection, which involves detecting errors at a receiver. According to one type of scheme, a transmitter calculates a code for transmission data using an algorithm. The code is appended to the data and both the code and the data are transmitted to the receiver. The receiver calculates another code from received data using the same algorithm. If the codes do not match, then one or more errors have been introduced into the transmitted data during transmission.
One algorithm for error detection uses polynomials to generate Cyclic Redundancy Check (CRC) codes. A CRC code, also typically referred to as a CRC value or simply a CRC, is the remainder of the division of data by a polynomial, called a generator polynomial. CRC logic which generates a CRC may be implemented using hardware, such as exclusive-or (XOR) gates.
Prior to processing by CRC logic, a data block may be aligned so that the next bits to be processed are moved into correct position. After alignment, one of multiple physical implementations of CRC logic, for different data block lengths and/or CRC types, may be selected. Common types of CRCs are CRC-16, CRC-32, and CRC-64, which have different associated lengths of codes. Finally, the aligned data block is sent to the selected CRC logic implementation to generate a CRC.
FIG. 1 is a block diagram of a conventional arrangement for generating CRCs. In the example shown, a barrel shifter 2 aligns an unaligned received data packet. The aligned data packet is then supplied to CRC logic 4 to produce a CRC. A disadvantage of using the barrel shifter 2 to align a data packet is that common implementations of barrel shifters require many logic gates.
FIG. 2 is a block diagram of another conventional arrangement, which includes CRC logic for generating a CRC based on different lengths of data packets. The CRC logic 20 has multiple XOR planes, generally designated 24, for generating CRCs for each of different lengths of data packets. An input 22 is coupled to the XOR planes 24, which in turn are coupled to a multiplexer 26. An output 28 of the multiplexer 26 is fed back to the XOR planes 24 via a feedback path 30.
In operation, an aligned data word is received at the input 22 and supplied to the XOR planes 24. Each XOR plane 24 generates a CRC, and the CRC generated by one of the XOR planes is selected by the multiplexer 26, based on a desired length 32, to produce an output CRC at 28. FIG. 2 shows CRC-32 logic 20 having N XOR planes 24 for producing N CRCs for respective different lengths of data packets. The multiplexer 26 is thus an N-to-1 multiplexer that selects one (1) CRC from the N CRCs.
As such, multiple XOR planes 24 are required, specifically one XOR plane for each supported data packet length.
FIG. 3 is a block diagram of a conventional arrangement for generating CRCs of different types. An input 41 is coupled to CRC logic of different types, such as CRC-32 logic 42, CRC-16 logic 43, and so on. Each implementation of CRC logic is in turn coupled to a multiplexer 46. An aligned data word is received at the input 41 and supplied to the CRC logic implementations 42, 43 to produce CRCs of respective types. A CRC is selected by the multiplexer 46, based on a desired CRC type 48, to produce the CRC at an output 50. As such, multiple physical CRC logic implementations 42, 43 of different types are required.
Thus, conventional techniques tend to use a respective dedicated physical CRC implementation for each data block length and CRC type to be supported. As the number of supported packet lengths increases, so does the physical area required to accommodate coding components. The timing of such conventional techniques also slows down due to an increased number of code types being generated.
This type of architecture is also used in other types of coding, such as data scrambling for instance.